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| ? semiconductor components industries, llc, 2012 august, 2012 ? rev. 4 1 publication order number: adp3212/d adp3212, ncp3218, NCP3218G 7-bit, programmable, 3-phase, mobile cpu synchronous buck controller the apd3212/ncp3218/NCP3218G is a highly efficient, multi ? phase, synchronous buck switching regulator controller. with its integrated drivers, the apd3212/ncp3218/NCP3218G is optimized for converting the notebook battery voltage into the core supply voltage required by high performance intel processors. an internal 7 ? bit dac is used to read a vid code directly from the processor and to set the cpu core voltage to a value within the range of 0.3 v to 1.5 v. the apd3212/ncp3218/NCP3218G is programmable for 1 ? , 2 ? , or 3 ? phase operation. the output signals ensure interleaved 2 ? or 3 ? phase operation. the apd3212/ncp3218/NCP3218G uses a multimode architecture run at a programmable switching frequency and optimized for efficiency depending on the output current requirement. the apd3212/ncp3218/NCP3218G switches between single ? and multi ? phase operation to maximize efficiency with all load conditions. the chip includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. the apd3212/ ncp3218/NCP3218G also provides accurate and reliable short ? circuit protection, adjustable current limiting, and a delayed power ? good output. the ic supports on ? the ? fly (otf) output voltage changes requested by the cpu. the apd3212/ncp3218/NCP3218G are specified over the extended commercial temperature range of ? 40 c to 100 c. the adp3212 is available in a 48 ? lead qfn 7x7mm 0.5mm pitch package. the ncp3218/NCP3218G is available in a 48 ? lead qfn 6x6mm 0.4mm pitch package. adp3212/ncp3218 has 1.1 v vboot voltage, while NCP3218G has 987.5 mv vboot voltage. except for the packages and vboot voltages, the apd3212/ncp3218/ NCP3218G are identical. apd3212/ncp3218/NCP3218G are halogen ? free, pb ? free and rohs compliant. features ? single ? chip solution ? fully compatible with the intel ? imvp ? 6.5 specifications ? selectable 1 ? , 2 ? , or 3 ? phase operation with up to 1 mhz per phase switching frequency ? phase 1 and phase 2 integrated mosfet drivers ? input voltage range of 3.3 v to 22 v ? guaranteed 8 mv worst ? case dif ferentially sensed core voltage error over temperature ? automatic power ? saving mode maximizes efficiency with light load during deeper sleep operation ? active current balancing between output phases ? independent current limit and load line setting inputs for additional design flexibility ? built ? in power ? good blanking supports voltage identification (vid) on ? the ? fly (otf) transients ? 7 ? bit, digitally programmable dac with 0.3 v to 1.5 v output ? short ? circuit protection with programmable latchoff delay ? clock enable output delays the cpu clock until the core voltage is stable ? output power or current monitor options ? 48 ? lead qfn 7x7mm (adp3212), 48 ? lead qfn 6x6mm (ncp3218/NCP3218G) ? vboot = 1.1 v (adp3212/ncp3218) vboot = 987.5 mv (NCP3218G) ? these are pb ? free devices ? fully rohs compliant applications ? notebook power supplies for next ? generation intel processors http://onsemi.com qfn48 case 485aj see detailed ordering and shipping information in the package dimensions section on page 33 of this data sheet. ordering information xxp321x awlyywwg 1 xxx = specific device code (adp3212 or ncp3218/g) a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package marking diagram qfn48 case 485ba 48 1 148
adp3212, ncp3218, NCP3218G http://onsemi.com 2 pin assignment 1 adp3212 ncp3218 (top view) en pwrgd ilim fbrtn fb comp gnd ttsns rpm swfb3 cscomp pwm3 cssum rt lline csref ramp bst2 drvh2 sw2 drvl2 pgnd pvcc swfb1 sw1 drvh1 bst1 vcc vrtt vid6 vid5 vid4 vid3 vid2 vid1 vid0 varfreq imon iref ph1 dprslp ph0 swfb2 drvl1 trdet clken psi od3 figure 1. functional block diagram number of phases vid dac vid6 vid5 vid4 vid3 vid2 vid1 vid0 fbrtn start up delay open drain pwrgd start up delay pwrgd pwrgd open drain + ? + ? csref dac + 200 mv dac ? 300 mv soft transient delay delay disable dac ? + csref cssum cscomp ilim thermal throttle control ttsense vrtt + ? ovp csref 1.55 v + ? _ + lline ref ref + + vea fb comp uvlo shutdown and bias vcc en gnd oscillator rpm rt ramp pwm3 current balancing circuit swfb1 swfb2 swfb3 imon dprslp psi and dprslp logic iref trdet generator current monitor current monitor bst1 drvh1 current limit circuit ocp shutdown delay sw1 pgnd drvl1 pvcc bst2 drvh2 sw2 drvl2 pvcc pgnd driver logic precision reference precision reference soft start varfreq ph0 ph1 clken trdet clken clken od3 psi adp3212, ncp3218, NCP3218G http://onsemi.com 3 absolute maximum ratings parameter rating unit v cc , pv cc1 , pv cc2 ? 0.3 to +6.0 v fbrtn, pgnd1, pgnd2 ? 0.3 to +0.3 v bst1, bst2, drvh1, drvh2 dc t < 200 ns ? 0.3 to +28 ? 0.3 to +33 v bst1 to pv cc , bst2 to pv cc dc t < 200 ns ? 0.3 to +22 ? 0.3 to +28 v bst1 to sw1, bst2 to sw2 ? 0.3 to +6.0 v sw1, sw2 dc t < 200 ns ? 1.0 to +22 ? 6.0 to +28 v drvh1 to sw1, drvh2 to sw2 ? 0.3 to +6.0 v drvl1 to pgnd1, drvl2 to pgnd2 dc t < 200 ns ? 0.3 to +6.0 ? 5.0 to +6.0 v ramp (in shutdown) ? 0.3 to +22 v all other inputs and outputs ? 0.3 to +6.0 v storage temperature range ? 65 to +150 c operating ambient temperature range ? 40 to +100 c operating junction temperature 125 c thermal impedance ( ja ) 2 ? layer board 30.5 c/w lead temperature soldering (10 sec) infrared (15 sec) 300 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device is esd sensitive. use standard esd precautions when handling. pin assignment pin no. mnemonic description 1 en enable input. driving this pin low shuts down the chip, disables the driver outputs, pulls pwrgd and vrtt low, and pulls clken high. 2 pwrgd power ? good output. open ? drain output. a low logic state means that the output voltage is outside of the vid dac defined range. 3 imon current monitor output. this pin sources a current proportional to the output load current. a resistor to fbrtn sets the current monitor gain. 4 clken clock enable output. open ? drain output. a low logic state enables the cpu internal pll clock to lock to the external clock. 5 fbrtn feedback return input/output. this pin remotely senses the cpu core voltage. it is also used as the ground return for the vid dac and the voltage error amplifier blocks. 6 fb voltage error amplifier feedback input. the inverting input of the voltage error amplifier. 7 comp voltage error amplifier output and frequency compensation point. 8 trdet transient detect output. this pin is pulled low when a load release transient is detected. during repetitive load transients at high frequencies, this circuit optimally positions the maximum and minimum output voltage into a specified loadline window. 9 varfreq variable frequency enable input. a high logic state enabl es the pwm clock frequency to vary with vid code. 10 vrtt voltage regulator thermal throttling output. logic high state indicates that the voltage regulator temperature at the remote sensing point exceeded a set alarm threshold level. adp3212, ncp3218, NCP3218G http://onsemi.com 4 pin assignment pin no. description mnemonic 11 ttsns thermal throttling sense and crowbar disable input. a re sistor divider where the upper resistor is connected to vcc, the lower resistor (ntc thermistor) is connec ted to gnd, and the center point is connected to this pin and acts as a temperature sensor half bridge. c onnecting ttsns to gnd disables the thermal throttling function and disables the crowbar, or overvo ltage protection (ovp), feature of the chip. 12 gnd analog and digital signal ground. 13 iref this pin sets the internal bias currents. a 80 k resistor is connected from this pin to ground. 14 rpm rpm mode timing control input. a resistor between this pin to ground sets the rpm mode turn ? on threshold voltage. 15 rt multi ? phase frequency setting input. an external resistor connected between this pin and gnd sets the oscillator frequency of the device when operating in multi ? phase pwm mode threshold of the converter. 16 ramp pwm ramp slope setting input. an external resistor from the converter input voltage node to this pin sets the slope of the internal pwm stabilizing ramp used for phase ? current balancing. 17 lline output load line programming input. the center point of a resistor divider between csref and cscomp is connected to this pin to set the load line slope. 18 csref current sense reference input. this pin must be connected to the common point of the output inductors. the node is shorted to gnd through an internal switch when the chip is disabled to provide soft stop transient control of the converter output voltage. 19 cssum current sense summing input. external resistors from each switch node to this pin sum the inductor currents to provide total current information. 20 cscomp current sense compensation point. a resistor and capacitor from this pin to cssum determine the gain of the current ? sense amplifier and the positioning loop response time. 21 ilim current limit setpoint. an external resistor from this pin to cscomp sets the current limit threshold of the converter. 22 od3 multi ? phase output disable logic output. this pin is actively pulled low when the apd3212/ncp3218/ NCP3218G enters single ? phase mode or during shutdown. connect this pin to the sd inputs of the phase ? 3 mosfet drivers. 23 pwm3 logic ? level pwm output for phase 3. connect to the input of an external mosfet driver such as the adp3611. 24 swfb3 current balance input for phase 3. input for measuring the current level in phase 3. swfb3 should be left open for 1 or 2 phase configuration. 25 bst2 high ? side bootstrap supply for phase 2. a capacitor from this pin to sw2 holds the bootstrapped voltage while the high ? side mosfet is on. 26 drvh2 high ? side gate drive output for phase 2. 27 sw2 current return for high ? side gate drive for phase 2. 28 swfb2 current balance input for phase 2. input for measuring the current level in phase 2. swfb2 should be left open for 1 phase configuration. 29 drvl2 low ? side gate drive output for phase 2. 30 pgnd low ? side driver power ground 31 drvl1 low ? side gate drive output for phase 1. 32 pvcc power supply input/output of low ? side gate drivers. 33 swfb1 current balance input for phase 1. input for measuring the current level in phase 1. 34 sw1 current return for high ? side gate drive for phase 1. 35 drvh1 high ? side gate drive output for phase 1. 36 bst1 high ? side bootstrap supply for phase 1. a capacitor from this pin to sw1 holds the bootstrapped voltage while the high ? side mosfet is on. 37 vcc power supply input/output of the controller. 38 ph1 phase number configuration input. connect to vcc for 3 phase configuration. 39 ph0 phase number configuration input. connect to gnd for 1 phase configuration. connect to vcc for multi ? phase configuration. 40 dprslp deeper sleep control input. 41 psi power state indicator input. pulling this pin to gnd forces the apd3212/ncp3218/NCP3218G to operate in single ? phase mode. 42 to 48 vid6 to vid0 voltage identification dac inputs. when in normal operation mode, the dac output programs the fb regulation voltage from 0.3 v to 1.5 v (see table 3). adp3212, ncp3218, NCP3218G http://onsemi.com 5 electrical characteristics v cc = pv cc = 5.0 v, fbrtn = pgnd = gnd = 0 v, h = 5.0 v, l = 0 v, en = varfreq = h, dprslp = l, psi = 1.05 v, v vid = v dac = 1.2000 v, t a = ? 40 c to 100 c, unless otherwise noted. (note 1) current entering a pin (sink current) has a positive sign. parameter symbol conditions min typ max units voltage control voltage error amplifier (veamp) fb, lline voltage range (note 2) v fb , v lline relative to csref = vdac ? 200 +200 mv fb, lline offset voltage (note 2) v osvea relative to csref = vdac ? 0.5 +0.5 mv lline bias current i lline ? 100 +100 na fb bias current i fb ? 1.0 +1.0 a lline positioning accuracy v fb ? v vid measured on fb relative to v vid , lline forced 80 mv below csref ? 77.5 ? 80 ? 82.5 mv comp voltage range (note 2) v comp 0.85 4.0 v comp current i comp comp = 2.0 v, csref = vdac fb forced 200 mv below csref fb forced 200 mv above csref ? 0.75 6 ma comp slew rate sr comp c comp = 10 pf, csref = vdac, open loop configuration fb forced 200 mv below csref fb forced 200 mv above csref 15 ? 20 v/ s gain bandwidth (note 2) gbw non ? inverting unit gain configuration, r fb = 1 k 20 mhz vid dac voltage reference vdac voltage range (note 2) see vid table 0 1.5 v vdac accuracy v fb ? v vid measured on fb (includes offset), relative to v vid v vid = 1.2000 v to 1.5000 v, t = ? 40 c to 100 c v vid = 0.3000 v to 1.1875 v, t = ? 40 c to 100 c ? 8.5 ? 7.5 +8.5 +7.5 mv vdac differential non ? linearity (note 2) ? 1.0 +1.0 lsb vdac line regulation v fb vcc = 4.75 v to 5.25 v 0.02 % vdac boot voltage (adp3212, ncp3218) v bootfb measured during boot delay period 1.100 v vdac boot voltage (NCP3218G) v bootfb measured during boot delay period 987.5 mv soft ? start delay (note 2) t dss measured from en pos edge to fb = 50 mv 200 s soft ? start time t ss measured from fb = 50 mv to fb settles to 1.1 v within 5% 1.4 ms boot delay t boot measured from fb settling to 1.1 v within 5% to clken neg edge 60 s vdac slew rate (note 2) soft ? start non ? lsb vid step, dprslp = h, slow c4 entry/exit non ? lsb vid step, dprslp = l, fast c4 exit lsb vid step, dvid transition 0.0625 0.25 1.0 0.4 lsb/ s fbrtn current i fbrtn ? 90 ? 200 a voltage monitoring and protection power good csref undervoltage threshold v uvcsref relative to nominal vdac voltage ? 240 ? 300 ? 360 mv csref overvoltage threshold v ovcsref relative to nominal vdac voltage 150 200 250 mv csref crowbar voltage threshold v cbcsref relative to fbrtn, v vid > 1.1 v relative to fbrtn, v vid 1.1 v 1.5 1.3 1.55 1.35 1.6 1.4 v 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. based on bench characterization data. 4. timing is referenced to the 90% and 10% points, unless otherwise noted. adp3212, ncp3218, NCP3218G http://onsemi.com 6 electrical characteristics v cc = pv cc = 5.0 v, fbrtn = pgnd = gnd = 0 v, h = 5.0 v, l = 0 v, en = varfreq = h, dprslp = l, psi = 1.05 v, v vid = v dac = 1.2000 v, t a = ? 40 c to 100 c, unless otherwise noted. (note 1) current entering a pin (sink current) has a positive sign. parameter units max typ min conditions symbol voltage monitoring and protection power good csref reverse voltage threshold v rvcsref relative to fbrtn, latchoff mode csref is falling csref is rising ? 370 ? 300 ? 75 ? 10 mv pwrgd low voltage v pwrgd i pwrgd(sink) = 4 ma 85 250 mv pwrgd high, leakage current i pwrgd v pwrdg = 5.0 v 1.0 a pwrgd startup delay t sspwrgd measured from clken neg edge to pwrgd pos edge 8.0 ms pwrgd latchoff delay t loffpwrgd measured from out ? off ? good ? window event to latchoff (switching stops) 120 s pwrgd propagation delay (note 3) t pdpwrgd measured from out ? off ? good ? window event to pwrgd neg edge 200 ns crowbar latchoff delay (note 2) t loffcb measured from crowbar event to latchoff (switching stops) 200 ns pwrgd masking time triggered by any vid change or ocp event 100 s csref soft ? stop resistance en = l or latchoff condition 70 current control current ? sense amplifier (csamp) cssum, csref common ? mode range (note 2) voltage range of interest 0 2.0 v cssum, csref offset voltage v oscsa csref ? cssum , t a = ? 40 c to 85 c ? 1.2 +1.2 mv cssum bias current i bcssum ? 20 +20 na csref bias current i bcsref ? 3.0 +3.0 a cscomp voltage range (note 2) voltage range of interest 0.05 2.0 v cscomp current i cscompsource cscomp = 2.0 v, cssum forced 200 mv below csref ? 750 a i cscompsink cssum forced 200 mv above csref 1.0 ma cscomp slew rate (note 2) c cscomp = 10 pf, csref = vdac, open loop configuration cssum forced 200 mv below csref cssum forced 200 mv above csref 20 ? 20 v/ s gain bandwidth (note 2) gbw csa non ? inverting unit gain configuration r fb = 1 k 20 mhz current monitoring and protection current reference iref voltage v ref r ref = 80 k to set i ref = 20 a 1.55 1.6 1.65 v current limiter (ocp) current limit (ocp) threshold v limth measured from cscomp to csref, r lim = 1.5 k , 3 ? ph configuration, psi = h 3 ? ph configuration, psi = l 2 ? ph configuration, psi = h 2 ? ph configuration, psi = l 1 ? ph configuration ? 75 ? 22 ? 75 ? 36 ? 75 ? 90 ? 30 ? 90 ? 45 ? 90 ? 106 ? 38 ? 106 ? 54 ? 106 mv current limit latchoff delay measured from ocp event to pwrgd de ? assertion 120 s 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. based on bench characterization data. 4. timing is referenced to the 90% and 10% points, unless otherwise noted. adp3212, ncp3218, NCP3218G http://onsemi.com 7 electrical characteristics v cc = pv cc = 5.0 v, fbrtn = pgnd = gnd = 0 v, h = 5.0 v, l = 0 v, en = varfreq = h, dprslp = l, psi = 1.05 v, v vid = v dac = 1.2000 v, t a = ? 40 c to 100 c, unless otherwise noted. (note 1) current entering a pin (sink current) has a positive sign. parameter units max typ min conditions symbol current monitor current gain accuracy i mon /i lim measured from ilim to imon i lim = ? 20 a i lim = ? 10 a i lim = ? 5 a 3.7 3.6 3.5 4.0 4.0 4.0 4.3 4.4 4.5 ? imon clamp voltage v maxmon relative to fbrtn, ilimp = ? 30 a 1.0 1.15 v pulse width modulator clock oscillator rt voltage v rt varfreq = high, r t = 125 k , v vid = 1.5000 v varfreq = low see also v rt (v vid ) formula 1.125 0.9 1.25 1.0 1.375 1.1 v pwm clock frequency range (note 2) f clk operation of interest 0.3 3.0 mhz pwm clock frequency f clk t a = +25 c, v vid = 1.2000 v r t = 72 k r t = 120 k r t = 180 k 1100 700 500 1257 800 550 1400 900 600 khz ramp generator ramp voltage v ramp en = high, i ramp = 60 a en = low 0.9 1.0 v in 1.1 v ramp current range (note 2) i ramp en = high en = low, ramp = 19 v 1.0 ? 1.0 100 +1.0 a pwm comparator pwm comparator offset (note 2) v osrpm v ramp ? v comp 3.0 mv rpm comparator rpm current i rpm v vid = 1.2 v, r t = 215 k see also i rpm (r t ) formula ? 9.0 a rpm comparator offset (note 2) v osrpm v comp ? (1 + v rpmth ) 3.0 mv epwm clock sync trigger threshold (note 2) relative to comp sampled t clk time earlier 3 ? phase configuration 2 ? phase configuration 1 ? phase configuration 350 400 450 mv trdet trigger threshold (note 2) relative to comp sampled t clk time earlier 3 ? phase configuration 2 ? phase configuration 1 ? phase configuration ? 450 ? 500 ? 600 mv trdet low voltage (note 2) v ltrdet logic low, i trdet sink = 4 ma 30 300 mv trdet leakage current i htrdet logic high, v trdet = vcc 5.0 a switch amplifier sw common mode range (note 2) v sw(x)cm operation of interest for current sensing ? 600 +200 mv swfb input resistance r sw(x) sw x = 0 v, swfb = 0 v 20 35 50 k zero current switching comparator sw zcs threshold v dcm(sw1) dcm mode, dprslp = 3.3 v ? 6.0 mv 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. based on bench characterization data. 4. timing is referenced to the 90% and 10% points, unless otherwise noted. adp3212, ncp3218, NCP3218G http://onsemi.com 8 electrical characteristics v cc = pv cc = 5.0 v, fbrtn = pgnd = gnd = 0 v, h = 5.0 v, l = 0 v, en = varfreq = h, dprslp = l, psi = 1.05 v, v vid = v dac = 1.2000 v, t a = ? 40 c to 100 c, unless otherwise noted. (note 1) current entering a pin (sink current) has a positive sign. parameter units max typ min conditions symbol zero current switching comparator masked off ? time t offmskd measured from drvh1 neg edge to drvh1 pos edge at operation max frequency 600 ns system i/o buffers vid[6:0], dprslp, psi inputs input voltage refers to driving signal level logic low logic high 0.7 0.3 v input current v = 0.2 v, vid[6:0], dprslp (active pulldown to gnd) psi (active pullup to vcc) ? 1.0 1.0 a vid delay time (note 2) any vid edge to fb change 10% 200 ns varfreq input voltage refers to driving signal level logic low logic high 4.0 0.7 v input current 1.0 a en input input voltage refers to driving signal level logic low logic high 1.9 0.4 v input current en = l or en = h (static) 0.8 v < en < 1.6 v (during transition) 10 ? 70 na a ph1, ph0 inputs input voltage refers to driving signal level logic low logic high 4.0 0.5 v input current 1.0 a clken output output low voltage logic low, i sink = 4 ma 60 200 mv output high, leakage current logic high, v clken = vcc 1.0 a pwm3, od3 outputs output voltage logic low, i sink = 400 a logic high, i source = ? 400 a 4.0 10 5.0 100 mv v thermal monitoring and protection ttsns voltage range (note 2) 0 5.0 v ttsns threshold vcc = 5.0 v, ttsns is falling 2.45 2.5 2.55 v ttsns hysteresis 95 mv ttsns bias current ttsns = 2.6 v ? 2.0 2.0 a vrtt output voltage v vrtt logic low, i vrtt(sink) = 400 a logic high, i vrtt(source) = ? 400 a 4.5 10 5.0 100 mv v supply supply voltage range v cc 4.5 5.5 v supply current en = high en = 0 v 7 10 10 150 ma a vcc ok threshold v ccok vcc is rising 4.4 4.5 v vcc uvlo threshold v ccuvlo vcc is falling 4.0 4.15 v 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. based on bench characterization data. 4. timing is referenced to the 90% and 10% points, unless otherwise noted. adp3212, ncp3218, NCP3218G http://onsemi.com 9 electrical characteristics v cc = pv cc = 5.0 v, fbrtn = pgnd = gnd = 0 v, h = 5.0 v, l = 0 v, en = varfreq = h, dprslp = l, psi = 1.05 v, v vid = v dac = 1.2000 v, t a = ? 40 c to 100 c, unless otherwise noted. (note 1) current entering a pin (sink current) has a positive sign. parameter units max typ min conditions symbol supply vcc hysteresis (note 2) 150 mv high ? side mosfet driver pullup resistance, sourcing current (note 3) bst = pvcc 1.8 3.3 pulldown resistance, sinking current (note 3) bst = pvcc 1.0 2.0 transition times tr drvh tf drvh bst = pvcc, c l = 3 nf, figure 2 bst = pvcc, c l = 3 nf, figure 2 15 13 30 25 ns dead delay times tpdh drvh bst = pvcc, figure 2 15 30 40 ns bst quiescent current en = l (shutdown) en = h, no switching 1.0 200 10 a low ? side mosfet driver pullup resistance, sourcing current (note 3) 1.7 2.8 pulldown resistance, sinking current (note 3) 0.8 1.7 transition times tr drvl tf drvl c l = 3 nf, figure 2 c l = 3 nf, figure 2 15 14 35 35 ns propagation delay times tpdh drvl c l = 3 nf, figure 2 11 30 ns sw transition timeout t tosw drvh = l, sw = 2.5 v 100 250 350 ns sw off threshold v offsw 2.5 v pvcc quiescent current en = l (shutdown) en = h, no switching 1.0 170 10 a bootstrap rectifier switch on resistance (note 3) en = l or en = h and drvl = h 4.0 6.0 8.0 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. based on bench characterization data. 4. timing is referenced to the 90% and 10% points, unless otherwise noted. figure 2. timing diagram (note 4) drvh (with respect to sw) drvl sw 1.0 v tf drvh v th v th tpdh drvl tr drvl tpdh drvh tr drvh tf drvl adp3212, ncp3218, NCP3218G http://onsemi.com 10 test circuits figure 3. closed ? loop output voltage accuracy figure 4. current sense amplifier, v os figure 5. positioning accuracy adp3212 drvl2 pgnd drvl1 pvcc swfb1 sw1 drvh1 bst1 sw2 swfb2 vid6 ph1 dprslp pwrgd imon fbrtn fb comp varfreq en vrtt rpm rt ramp lline csref cssum cscomp ilim iref 1 48 7 ? bit code 5 v 3.3 v 100 nf ph2 vcc drvh2 bst2 pwm3 swfb3 ttsns gnd adp3212 vcc 37 20 19 18 12 cscomp cssum csref gnd + ? 1.0 v 100 nf 5.0 v adp3212 vcc 37 7 6 18 12 comp fb lline gnd + ? 1.0 v 5.0 v csref 17 vid dac 1 k 80 k 20 k vid5 vid4 vid3 vid2 vid1 vid0 clken trdet od3 psi 39 k 1 k v os cscomp 1.0 v 40 v v fb fb v v fb v 0mv 10 k v adp3212, ncp3218, NCP3218G http://onsemi.com 11 typical performance characteristics v vid = 1.5 v, t a = 20 c to 100 c, unless otherwise noted. output voltage en 1 4 1 : 0.5 v/div 2 : 2 v/div 3 : 5 v/div 4 : 5 v/div 4 ms/div cpu mode pwrgd clken output voltage en 1 2 1 : 0.5 v/div 2 : 2 v/div 3 : 5 v/div 4 : 5 v/div 1 ms/div gpu mode pwrgd clken output voltage en 1 2 3 4 1 : 0.5 v/div 2 : 2 v/div 3 : 2 v/div 4 : 2 v/div 200 ms/div 1 a load pwrgd clken figure 6. switching frequency vs. vid output voltage in pwm mode figure 7. per phase switching frequency vs. rt resistance vid output voltage (v) rt resistance (k ) 1.50 1.25 1.00 0.75 0.50 0.25 0 50 100 150 200 250 350 400 1000 100 10 100 1000 figure 8. startup in gpu mode figure 9. startup in cpu mode figure 10. shutdown per phase switching frequency (khz) switching frequency (khz) 300 varfreq = 0 v varfreq = 5 v rt = 187 k 2 phase mode vid = 1.4125 v vid = 1.2125 v vid = 1.1 v vid = 0.8125 v vid = 0.6125 v 3 4 2 3 adp3212, ncp3218, NCP3218G http://onsemi.com 12 typical performance characteristics v vid = 1.5 v, t a = 20 c to 100 c, unless otherwise noted. sw1 sw3 1 2 3 4 1: 10 v/div 2: 10 v/div 3: 10 v/div 4: 2 v/div 4 ms/div sw2 dprslp sw1 sw3 1 2 3 4 1 : 10 v/div 2 : 10 v/div 3 : 10 v/div 4 : 0.5 v/div 4 ms/div sw2 psi sw1 sw3 1 2 3 4 1 : 10 v/div 2 : 10 v/div 3 : 10 v/div 4 : 2 v/div 4 ms/div sw2 dprslp sw1 sw3 1 2 3 4 1 : 10 v/div 2 : 10 v/div 3 : 10 v/div 4 : 0.5 v/div 4 ms/div sw2 psi sw1 sw3 1 2 3 4 1: 10 v/div 2: 10 v/div 3: 10 v/div 4: 2 v/div 4 ms/div sw2 dprslp sw1 sw3 1 2 3 4 1: 10 v/div 2: 10 v/div 3: 10 v/div 4: 2 v/div 4 ms/div sw2 dprslp figure 11. dprslp transition with psi = high figure 12. psi transition with dprslp = low figure 13. dprslp transition with psi = high figure 14. psi transition with dprslp = low figure 15. dprslp transition with psi = low figure 16. dprslp transition with psi = low adp3212, ncp3218, NCP3218G http://onsemi.com 13 theory of operation the apd3212/ncp3218/NCP3218G combines multi ? mode pulse ? width modulated (pwm) control and ramp ? pulse modulated (rpm) control with multi ? phase logic outputs for use in single ? , dual ? phase, or triple ? phase synchronous buck cpu core supply power converters. the internal 7 ? bit vid dac conforms to the intel imvp ? 6.5 specifications. multi ? phase operation is important for produc ing the high currents and low voltages demanded by today?s microprocessors. handling high currents in a single ? phase converter would put too high of a thermal stress on system components such as the inductors and mosfets. the multimode control of the apd3212/ncp3218/ NCP3218G is a stable, high performance architecture that includes ? current and thermal balance between phases. ? high speed response at the lowest possible switching frequency and minimal count of output decoupling capacitors. ? minimized thermal switching losses due to lower frequency operation. ? high accuracy load line regulation. ? high current output by supporting 2 ? phase or 3 ? phase operation. ? reduced output ripple due to multi ? phase ripple cancellation. ? high power conversion efficiency with heavy and light loads. ? increased immunity from noise introduced by pc board layout constraints. ? ease of use due to independent component selection. ? flexibility in design by allowing optimization for either low cost or high performance. number of phases the number of operational phases can be set by the user. tying the ph1 pin to the gnd pin forces the chip into single ? phase operation. tying ph0 to gnd and ph1 to vcc forces the chip into 2 ? phase operation. tying ph0 and ph1 to vcc forces the chip in 3 ? phase operation. ph0 and ph1 should be hard wired to vcc or gnd. the apd3212/ncp3218/NCP3218G switches between single phase and multi ? phase operation with psi and dprslp to optimize power conversion efficiency. table 1 summarizes ph0 and ph1. table 1. phase number configuration ph0 ph1 number of phases configured 0 0 1 1 0 1 (gpu mode) 0 1 2 1 1 3 in mulit ? phase configuration, the timing relationship between the phases is determined by internal circuitry that monitors the pwm outputs. because each phase is monitored independently, operation approaching 100% duty cycle is possible. in addition, more than one output can be active at a time, permitting overlapping phases. operation modes the number of phases can be static (see the number of phases section) or dynamically controlled by system signals to optimize the power conversion efficiency with heavy and light loads. if apd3212/ncp3218/NCP3218G is configured for mulit ? phase configuration, during a vid transient or with a heavy load condition (indicated by dprslp being low and psi being high), the apd3212/ncp3218/NCP3218G runs in multi ? phase, interleaved pwm mode to achieve minimal v core output voltage ripple and the best transient performance possible. if the load becomes light (indicated by psi being low or dprslp being high), apd3212/ ncp3218/NCP3218G switches to single ? phase mode to maximize the power conversion efficiency. in addition to changing the number of phases, the apd3212/ncp3218/NCP3218G is also capable of dynamically changing the control method. in dual ? phase operation, the apd3212/ncp3218/NCP3218G runs in pwm mode, where the switching frequency is controlled by the master clock. in single ? phase operation (commanded by the dprslp high state), the apd3212/ncp3218/ NCP3218G runs in rpm mode, where the switching frequency is controlled by the ripple voltage appearing on the comp pin. in rpm mode, the drvh1 pin is driven high each time the comp pin voltage rises to a voltage limit set by the vid voltage and an external resistor connected between the rpm pin and gnd. in rpm mode, the apd3212/ncp3218/NCP3218G turns off the low ? side (synchronous rectifier) mosfet when the inductor current drops to 0. turning off the low ? side mosfets at the zero current crossing prevents reversed inductor current build up and breaks synchronous operation of high ? and low ? side switches. due to the asynchronous operation, the switching frequency becomes slower as the load current decreases, resulting in good power conversion efficiency with very light loads. table 2 summarizes how the apd3212/ncp3218/ NCP3218G dynamically changes the number of active phases and transitions the operation mode based on system signals and operating conditions. gpu mode the apd3212/ncp3218/NCP3218G can be used to power imvp ? 6.5 gmch. to configure the apd3212/ ncp3218/NCP3218G in gpu, connect ph1 to vcc and connect ph0 to gnd. in gpu mode, the apd3212/ncp3218/NCP3218G operates in single phase only. in gpu mode, the boot voltage is disabled. during startup, the output voltage ramps up to the programmed vid voltage. there is no other difference between gpu mode and normal cpu mode. adp3212, ncp3218, NCP3218G http://onsemi.com 14 table 2. phase number and operation modes (note 1) psi no. dprslp vid transition (note 2) current limit no. of phases selected by the user no. of phases in operation operation modes (note 3) * * yes * n [3,2 or 1] n pwm, ccm only 1 0 no * n [3,2 or 1] n pwm, ccm only 0 0 no no * 1 rpm, ccm only 0 0 no yes n [3,2 or 1] n pwm, ccm only * 1 no no * 1 rpm, automatic ccm/dcm * 1 no yes * 1 pwm, ccm only 1. * = don?t care. 2. vid transient period is the time following any vid change, including entry into and exit from deeper sleep mode. the duration of vid transient period is the same as that of pwrgd masking time. 3. ccm stands for continuous current mode, and dcm stands for discontinuous current mode. figure 17. single ? phase rpm mode operation q s rd flip ? flop 1 v s rd vdc drvh drvl gate driver sw vcc l l load comp fb fbrtn cscomp cssum csref drvl1 sw1 drvh1 vrmp bst bst1 drvh drvl gate driver sw vcc drvl2 sw2 drvh2 bst bst2 q 400 ns r2 r1 r1 r2 1 v 30 mv in dcm lline in dcm + ? + ? + + swfb1 swfb2 flip ? flop r ph r ph r i r i 100 q q i r = a r x i ramp c r v cs r a c a c fb c b r fb r cs c cs 100 adp3212, ncp3218, NCP3218G http://onsemi.com 15 figure 18. 3 ? phase pwm mode operation bst drvh sw drvl in vcc q s rd gate driver clock oscillator flip ? flop + ? + ? 0.2 v l bst drvh sw drvl in vcc q s rd gate driver clock oscillator flip ? flop + ? + ? 0.2 v l bst drvh sw drvl in vcc q s rd gate driver clock oscillator flip ? flop + ? + ? 0.2 v l vcc ramp ? + _ + ? + + _ dac + + load bst1 drvh1 sw1 drvl1 bst2 drvh2 sw2 drvl2 swfb1 swfb2 pwm3 swfb3 csref cssum cscomp lline fbrtn fb comp a d c r i r = a r x i ramp i r = a r x i ramp c r c r i r = a r x i ramp a d a d c a r a c b r b c fb 100 100 r l r l 100 r l r cs c cs r ph r ph r ph setting switch frequency master clock frequency in pwm mode when the apd3212/ncp3218/NCP3218G runs in pwm, the clock frequency is set by an external resistor connected from the rt pin to gnd. the frequency is constant at a given vid code but varies with the vid voltage: the lower the vid voltage, the lower the clock frequency. the variation of clock frequency with vid voltage maintains constant v core ripple and improves power conversion efficiency at lower vid voltages. figure 7 shows the relationship between clock frequency and vid voltage, parameterized by rt resistance. to determine the switching frequency per phase, divide the clock by the number of phases in use. switching frequency in rpm mode; single ? phase operation in single ? phase rpm mode, the switching frequency is controlled by the ripple voltage on the comp pin, rather than by the master clock. each time the comp pin voltage adp3212, ncp3218, NCP3218G http://onsemi.com 16 exceeds the rpm pin voltage threshold level determined by the vid voltage and the external resistor rpm resistor, an internal ramp signal is started and drvh1 is driven high. the slew rate of the internal ramp is programmed by the current entering the ramp pin. one ? third of the ramp current charges an internal ramp capacitor (5 pf typical) and creates a ramp. when the internal ramp signal intercepts the comp voltage, the drvh1 pin is reset low. differential sensing of output voltage the apd3212/ncp3218/NCP3218G combines differential sensing with a high accuracy vid dac, referenced by a precision band gap source and a low offset error amplifier, to meet the rigorous accuracy requirement of the intel imvp ? 6.5 specification. in steady ? state mode, the combination of the vid dac and error amplifier maintain the output voltage for a worst ? case scenario within 8 mv of the full operating output voltage and temperature range. the cpu core output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the positive regulation point; the vcc remote sensing pin of the microprocessor. fbrtn should be connected directly to the negative remote sensing point; the v ss sensing point of the cpu. the internal vid dac and precision voltage reference are referenced to fbrtn and have a maximum current of 200 a for guaranteed accurate remote sensing. output current sensing the apd3212/ncp3218/NCP3218G includes a dedicated current sense amplifier (csa) to monitor the total output current of the converter for proper voltage positioning vs. load current and for over current detection. sensing the current delivered to the load is an inherently more accurate method than detecting peak current or sampling the current across a sense element, such as the low ? side mosfet. the current sense amplifier can be configured several ways, depending on system optimization objectives, and the current information can be obtained by: ? output inductor esr sensing without the use of a thermistor for the lowest cost. ? output inductor esr sensing with the use of a thermistor that tracks inductor temperature to improve accuracy. ? discrete resistor sensing for the highest accuracy. at the positive input of the csa, the csref pin is connected to the output voltage. at the negative input (that is, the cssum pin of the csa), signals from the sensing element (in the case of inductor dcr sensing, signals from the switch node side of the output inductors) are summed together by series summing resistors. the feedback resistor between the cscomp and cssum pins sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. the current information is then given as the voltage difference between the cscomp and csref pins. this signal is used internally as a differential input for the current limit comparator. an additional resistor divider connected between the cscomp and csref pins with the midpoint connected to the lline pin can be used to set the load line required by the microprocessor specification. the current information to set the load line is then given as the voltage difference between the lline and csref pins. this configuration allows the load line slope to be set independent from the current limit threshold. if the current limit threshold and load line do not have to be set independently, the resistor divider between the cscomp and csref pins can be omitted and the cscomp pin can be connected directly to lline. to disable voltage positioning entirely (that is, to set no load line), lline should be tied to csref. to provide the best accuracy for current sensing, the csa has a low offset input voltage and the sensing gain is set by an external resistor ratio. active impedance control mode to control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between lline and csref, can be scaled to be equal to the required droop voltage. this droop voltage is calculated by multiplying the droop impedance of the regulator by the output current. this value is used as the control voltage of the pwm regulator. the droop voltage is subtracted from the dac reference output voltage, and the resulting voltage is used as the voltage positioning set point. the arrangement results in an enhanced feed forward response. current control mode and thermal balance the apd3212/ncp3218/NCP3218G has individual inputs for monitoring the current of each phase. the phase current information is combined with an internal ramp to create a current ? balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. the current balance information is independent from the total inductor current information used for voltage positioning described in the active impedance control mode section. the magnitude of the internal ramp can be set so that the transient response of the system is optimal. the apd3212/ncp3218/NCP3218G monitors the supply voltage to achieve feed forward control whenever the supply voltage changes. a resistor connected from the power input voltage rail to the ramp pin determines the slope of the internal pwm ramp. more detail about programming the ramp is provided in the application information section. external resistors are placed in series with the swfb1, swfb2, and swfb3 pins to create an intentional current imbalance. such a condition can exist when one phase has better cooling and supports higher currents the other phases. resistors rswsb1, rswfb2, and rswfb3 (see figure 25) can be used to adjust thermal balance. it is recommended to add these resistors during the initial design to make sure placeholders are provided in the layout. adp3212, ncp3218, NCP3218G http://onsemi.com 17 to increase the current in any given phase, users should make rswfb for that phase larger (that is, rswfb = 100 for the hottest phase and do not change it during balance optimization). increasing rswfb to 150 makes a substantial increase in phase current. increase each rswfb value by small amounts to achieve thermal balance starting with the coolest phase. if adjusting current balance between phases is not needed, rswfb should be 100 for all phases. figure 19. current balance resistors vdc phase 1 inductor swfb1 vdc phase 2 inductor vdc phase 3 inductor swfb2 swfb3 33 28 24 adp3212 r swfb3 r swfb2 r swfb1 voltage control mode a high ? gain bandwidth error amplifier is used for the voltage mode control loop. the non ? inverting input voltage is set via the 7 ? bit vid dac. the vid codes are listed in table 3. the non ? inverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. the output of the error amplifier is the comp pin, which sets the termination voltage of the internal pwm ramps. at the negative input, the fb pin is tied to the output sense location using r b , a resistor for sensing and controlling the output voltage at the remote sensing point. the main loop compensation is incorporated in the feedback network connected between the fb and comp pins. power ? good monitoring the power ? good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open ? drain output that can be pulled up through an external resistor to a voltage rail; not necessarily the same vcc voltage rail that is running the controller. a logic high level indicates that the output voltage is within the voltage limits defined by a range around the vid voltage setting. pwrgd goes low when the output voltage is outside of this range. following the imvp ? 6.5 specification, the pwrgd range is defined to be 300 mv less than and 200 mv greater than the actual vid dac output voltage. for any dac voltage less than 300 mv, only the upper limit of the pwrgd range is monitored. to prevent a false alarm, the power ? good circuit is masked during various system transitions, including a vid change and entrance into or exit out of deeper sleep. the duration of the pwrgd mask is set to approximately 130 s by an internal timer. if the voltage drop is greater than 200 mv during deeper sleep entry or slow deeper sleep exit, the duration of pwrgd masking is extended by the internal logic circuit. powerup sequence and soft ? start the power ? on ramp ? up time of the output voltage is set internally. the apd3212/ncp3218/NCP3218G steps sequentially through each vid code until it reaches the boot voltage. the powerup sequence, including the soft ? start is illustrated in figure 20. after en is asserted high, the soft ? start sequence starts. the core voltage ramps up linearly to the boot voltage. the apd3212/ncp3218/NCP3218G regulates at the boot voltage for approximately 90 s. after the boot time is over, clken is asserted low. before clken is asserted low, the vid pins are ignored. 9 ms after clken is asserted low, pwrgd is asserted high. figure 20. powerup sequence of apd3212/ncp3218/NCP3218G vcc = 5 v en pwrgd t boot v core clken v boot t cpu_pwrgd current limit the apd3212/ncp3218/NCP3218G compares the differential output of a current sense amplifier to a programmable current limit set point to provide the current limiting function. the current limit threshold is set by the user with a resistor connected from the ilim pin to cscomp. changing vid on ? the ? fly (otf) the apd3212/ncp3218/NCP3218G is designed to track dynamically changing vid code. as a consequence, the cpu vcc voltage can change without the need to reset the controller or the cpu. this concept is commonly referred to as vid otf transient. a vid otf can occur with either light or heavy load conditions. the processor alerts the controller that a vid change is occurring by changing the vid inputs in lsb incremental steps from the start code to the finish code. the change can be either upwards or downwards steps. adp3212, ncp3218, NCP3218G http://onsemi.com 18 when a vid input changes, the apd3212/ncp3218/ NCP3218G detects the change but ignores new code for a minimum of 400 ns. this delay is required to prevent the device from reacting to digital signal skew while the 7 ? bit vid input code is in transition. additionally, the vid change triggers a pwrgd masking timer to prevent a pwrgd failure. each vid change resets and retriggers the internal pwrgd masking timer. as listed in table 3, during a vid transient, the apd3212/ncp3218/NCP3218G forces pwm mode regardless of the state of the system input signals. for example, this means that if the chip is configured as a dual ? phase controller but is running in single ? phase mode due to a light load condition, a current overload event causes the chip to switch to dual ? phase mode to share the excessive load until the delayed current limit latchoff cycle terminates. in user ? set single ? phase mode, the apd3212/ncp3218/ NCP3218G usually runs in rpm mode. when a vid transition occurs, however, the apd3212/ncp3218/ NCP3218G switches to dual ? phase pwm mode. light load rpm dcm operation in single ? phase normal mode, dprslp is pulled low and the apd3208 operates in continuous conduction mode (ccm) over the entire load range. the upper and lower mosfets run synchronously and in complementary phase. see figure 21 for the typical waveforms of the apd3212/ncp3218/NCP3218G running in ccm with a 7 a load current. figure 21. single ? phase waveforms in ccm 3 1 2 4 400 ns/div output voltage switch node 5 v/div low ? side gate drive 5 v/div 5 a/div inductor current 20 mv/div if dprslp is pulled high, the apd3212/ncp3218/ NCP3218G operates in rpm mode. if the load condition is light, the chip enters discontinuous conduction mode (dcm). figure 22 shows a typical single ? phase buck with one upper fet, one lower fet, an output inductor, an output capacitor, and a load resistor. figure 23 shows the path of the inductor current with the upper fet on and the lower fet off. in figure 24, the high ? side fet is off and the low ? side fet is on. in ccm, if one fet is on, its complementary fet must be off; however, in dcm, both high ? and low ? side fets are off and no current flows into the inductor (see figure 25). figure 26 shows the inductor current and switch node voltage in dcm. in dcm with a light load, the apd3212/ncp3218/ NCP3218G monitors the switch node voltage to determine when to turn off the low ? side fet. figure 27 shows a typical waveform in dcm with a 1 a load current. between t 1 and t 2 , the inductor current ramps down. the current flows through the source drain of the low ? side fet and creates a voltage drop across the fet with a slightly negative switch node. as the inductor current ramps down to 0 a, the switch voltage approaches 0 v, as seen just before t 2 . when the switch voltage is approximately ? 6 mv, the low ? side fet is turned off. figure 26 shows a small, dampened ringing at t 2 . this is caused by the lc created from capacitance on the switch node, including the c ds of the fets and the output inductor. this ringing is normal. the apd3212/ncp3218/NCP3218G automatically goes into dcm with a light load. figure 27 shows the typical dcm waveform of the apd3212/ncp3218/NCP3218G. as the load increases, the apd3212/ncp3218/NCP3218G enters into ccm. in dcm, frequency decreases with load current. figure 28 shows switching frequency vs. load current for a typical design. in dcm, switching frequency is a function of the inductor, load current, input voltage, and output voltage. figure 22. buck topology figure 23. buck topology inductor current during t 0 and t 1 figure 24. buck topology inductor current during t 1 and t 2 figure 25. buck topology inductor current during t 2 and t 3 switch node l drvl drvh q1 q2 c output voltage load input voltage l c on off load l c on off load l c off off load adp3212, ncp3218, NCP3218G http://onsemi.com 19 figure 26. inductor current and switch node in dcm inductor current switch node voltage t 0 t 1 t 2 t 3 t 4 figure 27. single ? phase waveforms in dcm with 1 a load current 3 1 2 4 2 s/div switch node 5 v/div low ? side gate drive 5 v/div output voltage 20 mv/div inductor current 5 a/div figure 28. single ? phase ccm/dcm frequency vs. load current 400 0 014 load current (a) frequency (khz) 350 300 250 200 150 100 50 24681012 19 v input 9 v input output crowbar to prevent the cpu and other external components from damage due to overvoltage, the apd3212/ncp3218/ NCP3218G turns off the drvh1 and drvh2 outputs and turns on the drvl1 and drvl2 outputs when the output voltage exceeds the ovp threshold (1.55 v typical). turning on the low ? side mosfets forces the output capacitor to discharge and the current to reverse due to current build up in the inductors. if the output overvoltage is due to a drain ? source short of the high ? side mosfet, turning on the low ? side mosfet results in a crowbar across the input voltage rail. the crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the microprocessor from destruction. when the ovp feature is triggered, the apd3212/ ncp3218/NCP3218G is latched off. the latchoff function can be reset by removing and reapplying vcc to the apd3212/ncp3218/NCP3218G or by briefly pulling the en pin low. pulling ttsns to less than 1.0 v disables the overvoltage protection function. in this configuration, vrtt should be tied to ground. reverse voltage protection very large reverse current in inductors can cause negative v core voltage, which is harmful to the cpu and other output components. the apd3212/ncp3218/NCP3218G provides a reverse voltage protection (rvp) function without additional system cost. the v core voltage is monitored through the csref pin. when the csref pin voltage drops to less than ? 300 mv, the apd3212/ ncp3218/NCP3218G triggers the rvp function by disabling all pwm outputs and driving drvl1 and drvl2 low, thus turning off all mosfets. the reverse inductor currents can be quickly reset to 0 by dischar ging the built ? up energy in the inductor into the input dc voltage source via the forward ? biased body diode of the high ? side mosfets. the rvp function is terminated when the csref pin voltage returns to greater than ? 100 mv. sometimes the crowbar feature inadvertently causes output reverse voltage because turning on the low ? side mosfets results in a very large reverse inductor current. to prevent damage to the cpu caused from negative voltage, the apd3212/ncp3218/NCP3218G maintains its rvp monitoring function even after ovp latchoff. during ovp latchoff, if the csref pin voltage drops to less than ? 300 mv, the low ? side mosfets is turned off. drvl outputs are allowed to turn back on when the csref voltage recovers to greater than ? 100 mv. output enable and uvlo for the apd3212/ncp3218/NCP3218G to begin switching, the vcc supply voltage to the controller must be greater than the v ccok threshold and the en pin must be driven high. if the vcc voltage is less than the v ccuvlo threshold or the en pin is a logic low, the adp3212, ncp3218, NCP3218G http://onsemi.com 20 apd3212/ncp3218/NCP3218G shuts off. in shutdown mode, the controller holds the pwm outputs low, shorts the capacitors of the ss and pgdelay pins to ground, and drives the drvh and drvl outputs low. the user must adhere to proper power ? supply sequencing during startup and shutdown of the apd3212/ncp3218/ NCP3218G. all input pins must be at ground prior to removing or applying vcc, and all output pins should be left in high impedance state while vcc is off. thermal throttling control the apd3212/ncp3218/NCP3218G includes a thermal monitoring circuit to detect whether the temperature of the vr has exceeded a user ? defined thermal throttling threshold. the thermal monitoring circuit requires an external resistor divider connected between the vcc pin and gnd. the divider consists of an ntc thermistor and a resistor. to generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the ttsns pin. an internal comparator circuit compares the ttsns voltage to half the vcc threshold and outputs a logic level signal at the vrtt output when the temperature trips the user ? set alarm threshold. the vrtt output is designed to drive an external transistor that in turn provides the high current, open ? drain vrtt signal required by the imvp ? 6.5 specification. the internal vrtt comparator has a hysteresis of approximately 100 mv to prevent high frequency oscillation of vrtt when the temperature approaches the set alarm point. output current monitor the apd3212/ncp3218/NCP3218G has an output current monitor. the imon pin sources a current proportional to the inductor current. a resistor from imon pin to fbrtn sets the gain. a 0.1 f is added in parallel with r mon to filter the inductor ripple. the imon pin is clamped to prevent it from going above 1.15 v. table 3. vid code table vid6 vid5 vid4 vid3 vid2 vid1 vid0 output (v) 0 0 0 0 0 0 0 1.5000 v 0 0 0 0 0 0 0 1.5000 v 0 0 0 0 0 0 1 1.4875 v 0 0 0 0 0 1 0 1.4750 v 0 0 0 0 0 1 1 1.4625 v 0 0 0 0 1 0 0 1.4500 v 0 0 0 0 1 0 1 1.4375 v 0 0 0 0 1 1 0 1.4250 v 0 0 0 0 1 1 1 1.4125 v 0 0 0 1 0 0 0 1.4000 v 0 0 0 1 0 0 1 1.3875 v 0 0 0 1 0 1 0 1.3750 v 0 0 0 1 0 1 1 1.3625 v 0 0 0 1 1 0 0 1.3500 v 0 0 0 1 1 0 1 1.3375 v 0 0 0 1 1 1 0 1.3250 v 0 0 0 1 1 1 1 1.3125 v 0 0 1 0 0 0 0 1.3000 v 0 0 1 0 0 0 1 1.2875 v 0 0 1 0 0 1 0 1.2750 v 0 0 1 0 0 1 1 1.2625 v 0 0 1 0 1 0 0 1.2500 v 0 0 1 0 1 0 1 1.2375 v 0 0 1 0 1 1 0 1.2250 v 0 0 1 0 1 1 1 1.2125 v 0 0 1 1 0 0 0 1.2000 v 0 0 1 1 0 0 1 1.1875 v 0 0 1 1 0 1 0 1.1750 v 0 0 1 1 0 1 1 1.1625 v 0 0 1 1 1 0 0 1.1500 v 0 0 1 1 1 0 1 1.1375 v adp3212, ncp3218, NCP3218G http://onsemi.com 21 table 3. vid code table (continued) vid6 output (v) vid0 vid1 vid2 vid3 vid4 vid5 0 0 1 1 1 1 0 1.1250 v 0 0 1 1 1 1 1 1.1125 v 0 1 0 0 0 0 0 1.1000 v 0 1 0 0 0 0 1 1.0875 v 0 1 0 0 0 1 0 1.0750 v 0 1 0 0 0 1 1 1.0625 v 0 1 0 0 1 0 0 1.0500 v 0 1 0 0 1 0 1 1.0375 v 0 1 0 0 1 1 0 1.0250 v 0 1 0 0 1 1 1 1.0125 v 0 1 0 1 0 0 0 1.0000 v 0 1 0 1 0 0 1 0.9875 v 0 1 0 1 0 1 0 0.9750 v 0 1 0 1 0 1 1 0.9625 v 0 1 0 1 1 0 0 0.9500 v 0 1 0 1 1 0 1 0.9375 v 0 1 0 1 1 1 0 0.9250 v 0 1 0 1 1 1 1 0.9125 v 0 1 1 0 0 0 0 0.9000 v 0 1 1 0 0 0 1 0.8875 v 0 1 1 0 0 1 0 0.8750 v 0 1 1 0 0 1 1 0.8625 v 0 1 1 0 1 0 0 0.8500 v 0 1 1 0 1 0 1 0.8375 v 0 1 1 0 1 1 0 0.8250 v 0 1 1 0 1 1 1 0.8125 v 0 1 1 1 0 0 0 0.8000 v 0 1 1 1 0 0 1 0.7875 v 0 1 1 1 0 1 0 0.7750 v 0 1 1 1 0 1 1 0.7625 v 0 1 1 1 1 0 0 0.7500 v 0 1 1 1 1 0 1 0.7375 v 0 1 1 1 1 1 0 0.7250 v 0 1 1 1 1 1 1 0.7125 v 1 0 0 0 0 0 0 0.7000 v 1 0 0 0 0 0 1 0.6875 v 1 0 0 0 0 1 0 0.6750 v 1 0 0 0 0 1 1 0.6625 v 1 0 0 0 1 0 0 0.6500 v 1 0 0 0 1 0 1 0.6375 v 1 0 0 0 1 1 0 0.6250 v 1 0 0 0 1 1 1 0.6125 v 1 0 0 1 0 0 0 0.6000 v 1 0 0 1 0 0 1 0.5875 v 1 0 0 1 0 1 0 0.5750 v 1 0 0 1 0 1 1 0.5625 v 1 0 0 1 1 0 0 0.5500 v 1 0 0 1 1 0 1 0.5375 v 1 0 0 1 1 1 0 0.5250 v adp3212, ncp3218, NCP3218G http://onsemi.com 22 table 3. vid code table (continued) vid6 output (v) vid0 vid1 vid2 vid3 vid4 vid5 1 0 0 1 1 1 1 0.5125 v 1 0 1 0 0 0 0 0.5000 v 1 0 1 0 0 0 1 0.4875 v 1 0 1 0 0 1 0 0.4750 v 1 0 1 0 0 1 1 0.4625 v 1 0 1 0 1 0 0 0.4500 v 1 0 1 0 1 0 1 0.4375 v 1 0 1 0 1 1 0 0.4250 v 1 0 1 0 1 1 1 0.4125 v 1 0 1 1 0 0 0 0.4000 v 1 0 1 1 0 0 1 0.3875 v 1 0 1 1 0 1 0 0.3750 v 1 0 1 1 0 1 1 0.3625 v 1 0 1 1 1 0 0 0.3500 v 1 0 1 1 1 0 1 0.3375 v 1 0 1 1 1 1 0 0.3250 v 1 0 1 1 1 1 1 0.3125 v 1 1 0 0 0 0 0 0.3000 v 1 1 0 0 0 0 1 0.2875 v 1 1 0 0 0 1 0 0.2750 v 1 1 0 0 0 1 1 0.2625 v 1 1 0 0 1 0 0 0.2500 v 1 1 0 0 1 0 1 0.2375 v 1 1 0 0 1 1 0 0.2250 v 1 1 0 0 1 1 1 0.2125 v 1 1 0 1 0 0 0 0.2000 v 1 1 0 1 0 0 1 0.1875 v 1 1 0 1 0 1 0 0.1750 v 1 1 0 1 0 1 1 0.1625 v 1 1 0 1 1 0 0 0.1500 v 1 1 0 1 1 0 1 0.1375 v 1 1 0 1 1 1 0 0.1250 v 1 1 0 1 1 1 1 0.1125 v 1 1 1 0 0 0 0 0.1000 v 1 1 1 0 0 0 1 0.0875 v 1 1 1 0 0 1 0 0.0750 v 1 1 1 0 0 1 1 0.0625 v 1 1 1 0 1 0 0 0.0500 v 1 1 1 0 1 0 1 0.0375 v 1 1 1 0 1 1 0 0.0250 v 1 1 1 0 1 1 1 0.0125 v 1 1 1 1 0 0 0 0.0000 v 1 1 1 1 0 0 1 0.0000 v 1 1 1 1 0 1 0 0.0000 v 1 1 1 1 0 1 1 0.0000 v 1 1 1 1 1 0 0 0.0000 v 1 1 1 1 1 0 1 0.0000 v 1 1 1 1 1 1 0 0.0000 v 1 1 1 1 1 1 1 0.0000 v adp3212, ncp3218, NCP3218G http://onsemi.com 23 figure 29. typical dual ? phase application circuit vsssense vccsense csref csref a b ttsense ttsense vccsense vsssense vdc v5s v5s v3.3s v5s vdc vdc pwrgd dprslpvr vid6 vid5 vid4 vid3 vid2 vid1 vid0 vr_on vcore ph3_cs+ csref sw3 vrtt vcc(core) imvp ? 6.5 solution for penryn processor: 3 ? phase/55 ? 65 a nec tokin mpcg10lr45 vcc(core) rtn 4 pieces of panasonic sp cap (sd) or sanyo poscap. thermistor r4 should be placed close to the hot spot of the board. place r23 close to output inductor of phase 1. (optional) (optional) up to 32 pieces of mlcc, x5r, 0805, 6.3 v. nec tokin mpcg10lr45 note 2 note 2 1 2 3 6 5 7 8 2 1 1 2 1 2 sw2 j9 1 r73 dnp 12 c68 dnp 2 1 1 2 1 2 1 2 j22 clken# 1 r8 10 1 2 12 1 2 1 2 2 1 2 1 2 1 2 r71 0 1 2 c66 1 2 r68 69.8 k 1 2 3 6 5 7 8 2 1 l1 2 j7 con2 1 2 j24 imon 1 r61 12 r62 12 1 2 r69 dnp 1 2 r12 1.65 k 1 2 r17 280 k 1 2 12 r13 39.2 k 12 1 2 r74 0 12 1 2 r63 1 2 r26 115 k 1 2 12 1 2 r51 dnp 1 2 c67 1 2 r25 115 k 1 2 c4 1 2 c11 1n 1 2 r18 12 c6 330p 1 2 r56 dnp 12 l2 1 2 1 2 1 2 c15 12 1 2 1 2 1 c3 1 2 1 2 1 2 1 2 1 2 1 2 lfcsp48 u1 adp3212 ph0 39 sw2 27 41 dprslp 40 en 1 imon 3 4 comp 7 8 9 vid0 48 pwrgd 2 pwm3 23 cssum 19 rt 15 swfb2 28 drvl1 31 fb 6 lline 17 ramp 16 swfb3 24 fbrtn 5 vrtt 10 ttsns 11 pgnd 30 vcc 37 vid2 46 vid6 42 sw1 34 rpm 14 swfb1 33 drvl2 29 cscomp 20 22 pvcc 32 vid4 44 vid1 47 vid3 45 csref 18 vid5 43 ph1 38 gnd 12 iref 13 ilim 21 bst1 36 drvh1 35 drvh2 26 bst2 25 1 2 1 2 1 2 1 2 j8 sw1 1 1 2 d5 dnp 1 2 1 2 r14 4.53 k 1 2 1 2 1 2 c65 1 2 c22 12 12 1n 1 2 1 2 jp1 shortpin 1 2 1 2 1 2 c101 1n 1 2 r24 115 k 1 2 1 2 r32 0 1 2 c8 12p 1 2 r66 1 2 jp3 ph2 vcore cut 2 1 2 1 2 12 r52 dnp 1 2 ph1 vcore cut jp2 12 1 2 1n 1 2 r23 220kthermistor 5% 1 2 j2 trdet 1 j23 pwrgd 1 ntmfs4821n 3 6 5 7 8 2 4 1 1 2 1 2 1 2 1 2 1 2 1 2 r11 0 1 2 1 2 1 2 c70 1 2 1 2 1 2 rs1 dnp 12 12 r70 0 1 2 1 2 1 2 3 6 5 7 8 2 1 c13 1.5n 12 1 2 r60 7.50 k 1 2 1 2 1 1 2 1 2 j6 vss_s 1 1 2 1 2 1 2 rs2 dnp 12 1 2 1 2 r33 0 12 1 1 vdc 1 2 c103 1 2 3 6 5 7 8 2 4 1 1 2 1 2 1 2 c 3 6 5 7 8 2 4 1 1 2 1 2 1 2 ph3 vcore cut jp4 1 2 rs3 dnp 1 2 sw3 j26 1 l3 1 2 note 3 r65 dnp 1 2 r64 10 vcore csref ph3_cs+ note 2 1 2 u13 adp3611 in crowbar vcc drvl 6 8 v5s 1 2 c78 7 9 1 2 10 1 2 5 4 3 2 1 sw3 c14 2 2 0 r1 7.32 k c1 10n x7r dnp r72 x7r(0805) 1 f/16 v 2 1 r4 100 k therm.. 5% r45 3 k 4.7 f 10 f c20 10 f c19 10 f c18 10 f c17 q2 c16 0.47 j3 comp c12 150p r22 73.2 k 12 r20 dnp r19 0 165 k r21 dnp gnd sw drvh bst c14 1n r46 3 k 0.1 1 0.45 h/esr = 1.1 m r54 10 r53 10 r31 dnp r30 dnp r55 dnp 4 c104 860 pf r67 4.99 k c7 390 pf c5 1n 0.47 4 4 q9 ntmfs4846n q4 ntmfs4846n c29 dnp dnp d8 dnp c28 0.45 h/esr = 1.1 m 0.45 h/esr = 1.1 m 10 f c32 10 f c31 10 f c30 10 f c21 dnp d9 dnp dnp c79 r57 q20 ntmfs4821n q22 ntmfs4821n 0.47 q7 ntmfs4821n q8 ntmfs4821n r42 0 10 f c26 10 f 10 f c25 c24 10 f c23 c102 r16 402 k r15 280 k r27 80.6 k j5 vcc_s r10 100 r50 100 c33 10 f c34 10 f c35 10 f c36 10 f c37 10 f c38 10 f c39 10 f c40 10 f c41 10 f c42 10 f c43 10 f c44 10 f c45 10 f c46 10 f c47 10 f c48 10 f c49 10 f c50 10 f c51 10 f c52 10 f c53 10 f c54 10 f c55 10 f c56 10 f c57 10 f c58 10 f c59 10 f c60 10 f c61 10 f c62 10 f c63 10 f c64 10 f 330 f 330 f 1 c69 1 dnp 330 f 330 f psi od3 clken trdet varfreq sd drvlsd psi 4.7 f/ 16 v x5r (1206) 100 100 100 adp3212, ncp3218, NCP3218G http://onsemi.com 24 application information the design parameters for a typical imvp ? 6.5 ? compliant cpu core vr application are as follows: ? maximum input voltage (v inmax ) = 19 v ? minimum input voltage (v inmin ) = 8.0 v ? output voltage by vid setting (v vid ) = 1.05 v ? maximum output current (i o ) = 52 a ? droop resistance (r o ) = 1.9 m ? nominal output voltage at 40 a load (v ofl ) = 0.9512 v ? static output voltage drop from no load to full load ( v) = v onl ? v ofl = 1.05 v ? 0.9512 v = 98 mv ? maximum output current step ( i o ) = 52 a ? number of phases (n) = 2 ? switching frequency per phase ( ? sw ) = 300 khz ? duty cycle at maximum input voltage (d max ) = 0.13 v ? duty cycle at minimum input voltage (d min ) = 0.055 v setting the clock frequency for pwm in pwm operation, the apd3212/ncp3218/NCP3218G uses a fixed ? frequency control architecture. the frequency is set by an external timing resistor (rt). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. for a dual ? phase design, a clock frequency of 600 khz sets the switching frequency to 300 khz per phase. this selection represents the trade ? off between the switching losses and the minimum sizes of the output filter components. to achieve a 600 khz oscillator frequency at a vid voltage of 1.2 v, rt must be 181 k . alternatively, the value for rt can be calculated by using the following equation: r t v vid 1.0 v 2 n f sw 9pf 16 k (eq. 1) where: 9 pf and 16 k are internal ic component values. v vid is the vid voltage in volts. n is the number of phases. ? sw is the switching frequency in hertz for each phase. for good initial accuracy and frequency stability, it is recommended to use a 1% resistor. when varfreq pin is connected to ground, the switching frequency does not change with vid. the value for rt can be calculated by using the following equation. r t 1.0 v n 2 f sw 9pf 16 k (eq. 2) setting the switching frequency for rpm operation of phase 1 during the rpm operation of phase 1, the apd3212/ ncp3218/NCP3218G runs in pseudoconstant frequency if the load current is high enough for continuous current mode. while in dcm, the switching frequency is reduced with the load current in a linear manner. to save power with light loads, lower switching frequency is usually preferred during rpm operation. however, the v core ripple specification of imvp ? 6.5 sets a limitation for the lowest switching frequency. therefore, depending on the inductor and output capacitors, the switching frequency in rpm can be equal to, greater than, or less than its counterpart in pwm. a resistor from rpm to gnd sets the pseudo constant frequency as following: r rpm 2 r t v vid 1.0 v a r (1 d) v vid r r c r f sw 0.5 k (eq. 3) where: a r is the internal ramp amplifier gain. c r is the internal ramp capacitor value. r r is an external resistor on the rampadj pin to set the internal ramp magnitude. soft start and current limit latch ? off delay times inductor selection the choice of inductance determines the ripple current of the inductor. less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the mosfets. however, this allows the use of smaller ? size inductors, and for a specified peak ? to ? peak transient deviation, it allows less total output capacitance. conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger ? size inductors and more output capacitance for the same peak ? to ? peak transient deviation. for a multi ? phase converter, the practical value for peak ? to ? peak inductor ripple current is less than 50% of the maximum dc current of that inductor. equation 4 shows the relationship between the inductance, oscillator frequency, and peak ? to ? peak ripple current. equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. i r v vid (1 d min ) f sw l (eq. 4) l v vid r o 1 (n d min ) f sw v ripple (eq. 5) solving equation 5 for a 16 mv peak ? to ? peak output ripple voltage yields: l 1.05 v 1.9 m (1 2 0.055) 300 khz 16 mv 528 nh if the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. this iteration allows optimal transient response and minimum output decoupling. the smallest possible inductor should be used to minimize the number of output capacitors. choosing a 490 nh inductor is a good choice for a starting point, and it provides adp3212, ncp3218, NCP3218G http://onsemi.com 25 a calculated ripple current of 9.0 a. the inductor should not saturate at the peak current of 24.5 a, and it should be able to handle the sum of the power dissipation caused by the winding?s average current (20 a) plus the ac core loss. in this example, 330 nh is used. another important factor in the inductor design is the dcr, which is used for measuring the phase currents. too large of a dcr causes excessive power losses, whereas too small of a value leads to increased measurement error. for this example, an inductor with a dcr of 0.8 m is used. selecting a standard inductor after the inductance and dcr are known, select a standard inductor that best meets the overall design goals. it is also important to specify the inductance and dcr tolerance to maintain the accuracy of the system. using 20% tolerance for the inductance and 15% for the dcr at room temperature are reasonable values that most manufacturers can meet. power inductor manufacturers the following companies provide surface ? mount power inductors optimized for high power applications upon request: ? vishay dale electronics, inc. (605) 665 ? 9301 ? panasonic (714) 373 ? 7334 ? sumida electric company (847) 545 ? 6700 ? nec tokin corporation (510) 324 ? 4110 output droop resistance the design requires that the regulator output voltage measured at the cpu pins decreases when the output current increases. the specified voltage drop corresponds to the droop resistance (r o ). the output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low ? pass filter. the summing is implemented by the cs amplifier that is configured with resistor r ph(x) (summer) and resistors r cs and c cs (filters). the output resistance of the regulator is set by the following equations: r o r cs r ph(x) r sense (eq. 6) c cs l r sense r cs (eq. 7) where r sense is the dcr of the output inductors. either r cs or r ph(x) can be chosen for added flexibility. due to the current drive ability of the cscomp pin, the r cs resistance should be greater than 100 k . for example, initially select r cs to be equal to 200 k , and then use equation 7 to solve for c cs : c cs 330 nh 0.8 m 200 k 2.1 nf if c cs is not a standard capacitance, r cs can be tuned. for example, if the optimal c cs capacitance is 1.5 nf, adjust r cs to 280 k . for best accuracy, c cs should be a 5% npo capacitor. in this example, a 220 k is used for r cs to achieve optimal results. next, solve for r ph(x) by rearranging equation 6 as follows: r ph(x) 0.8 m 2.1 m 220 k 83.8 k the standard 1% resistor for r ph(x) is 86.6 k . inductor dcr temperature correction if the dcr of the inductor is used as a sense element and copper wire is the source of the dcr, the temperature changes associated with the inductor?s winding must be compensated for. fortunately, copper has a well ? known temperature coefficient (tc) of 0.39%/ c. if r cs is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductor?s dcr. due to the nonlinear nature of ntc thermistors, series resistors r cs1 and r cs2 (see figure 30) are needed to linearize the ntc and produce the desired temperature coefficient tracking. figure 30. temperature ? compensation circuit values adp3212 cscomp cssum csref + ? place as close as possible to nearest inductor to switch nodes keep this path as short as possible and well away from switch node lines r ph3 to v out sense r ph2 r ph1 r cs2 r cs1 c cs1 c cs2 r th 19 18 17 adp3212, ncp3218, NCP3218G http://onsemi.com 26 the following procedure and expressions yield values for r cs1 , r cs2 , and r th (the thermistor value at 25 c) for a given r cs value. 1. select an ntc to be used based on its type and value. because the value needed is not yet determined, start with a thermistor with a value close to r cs and an ntc with an initial tolerance of better than 5%. 2. find the relative resistance value of the ntc at two temperatures. the appropriate temperatures will depend on the type of ntc, but 50 c and 90 c have been shown to work well for most types of ntcs. the resistance values are called a (a is r th (50 c)/r th (25 c)) and b (b is r th (90 c)/r th (25 c)). note that the relative value of the ntc is always 1 at 25 c. 3. find the relative value of r cs required for each of the two temperatures. the relative value of r cs is based on the percentage of change needed, which is initially assumed to be 0.39%/ c in this example. the relative values are called r 1 (r 1 is 1/(1+ tc (t 1 ? 25))) and r 2 (r 2 is 1/(1 + tc (t 2 ? 25))), where tc is 0.0039, t 1 is 50 c, and t 2 is 90 c. 4. compute the relative values for r cs1 , r cs2 , and r th by using the following equations: r cs2 (a ? b) r 1 r 2 a (1 ? b) r 2 b (1 ? a) r 1 a (1 b) r 1 b (1 a) r 2 (a b) (eq. 8) r cs1 (1 a) 1 1 r cs2 a r 1 r cs2 r th 1 1 1 r cs2 1 r cs1 5. calculate r th = r th r cs , and then select a thermistor of the closest value available. in addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k r th(actual) r th(calculated) (eq. 9) 6. calculate values for r cs1 and r cs2 by using the following equations: r cs1 r cs k r cs1 (eq. 10) r cs2 r cs (1 k) (k r cs2 ) for example, if a thermistor value of 100 k is selected in step 1, an available 0603 ? size thermistor with a value close to r cs is the v ishay nths0603n04 ntc thermistor, which has resistance values of a = 0.3359 and b = 0.0771. using the equations in step 4, r cs1 is 0.359, r cs2 is 0.729, and r th is 1.094. solving for r th yields 241 k , so a thermistor of 220 k would be a reasonable selection, making k equal to 0.913. finally, r cs1 and r cs2 are found to be 72.1 k and 166 k . choosing the closest 1% resistor for r cs2 yields 165 k . to correct for this approximation, 73.3 k is used for r cs1 . c out selection the required output decoupling for processors and platforms is typically recommended by intel. for systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement. select the number of ceramics and determine the total ceramic capacitance (c z ). this is based on the number and type of capacitors used. keep in mind that the best location to place ceramic capacitors is inside the socket; however, the physical limit is twenty 0805 ? size pieces inside the socket. additional ceramic capacitors can be placed along the outer edge of the socket. a combined ceramic capacitor value of 200 f to 300 f is recommended and is usually composed of multiple 10 f or 22 f capacitors. ensure that the total amount of bulk capacitance (c x ) is within its limits. the upper limit is dependent on the vid otf output voltage stepping (voltage step, v v , in time, t v , with error of v err ); the lower limit is based on meeting the critical capacitance for load release at a given maximum load step, i o . the current version of the imvp ? 6.5 specification allows a maximum v core overshoot (v osmax ) of 10 mv more than the vid voltage for a step ? off load current. c x(min) l i o n r o v osmax i o v vid c z (eq. 11) where k ? ln v err v v (eq. 12) c x(max) l n k 2 r o 2 v v v vid 1 t v v vid v v n k r o l 2 1 c z adp3212, ncp3218, NCP3218G http://onsemi.com 27 to meet the conditions of these expressions and the transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance, r o . if the c x(min) is greater than c x(max) , the system does not meet the vid otf and/or the deeper sleep exit specifications and may require less inductance or more phases. in addition, the switching frequency may have to be increased to maintain the output ripple. for example, if 30 pieces of 10 f, 0805 ? size mlc capacitors (c z = 300 f) are used, the fastest vid voltage change is when the device exits deeper sleep, during which the v core change is 220 mv in 22 s with a setting error of 10 mv. if k = 3.1, solving for the bulk capacitance yields 330 nh 27.9 a 2 2.1 m 10 mv 27.9 a 1.4375 v 300 f 1.0 mf c x(max) 330 nh 220 mv 2 3.1 2 (2.1 m ) 2 1.4375 v c x(min) 1 22 s 1.4375v 2 3.1 2.1m 220 mv 490 nh 2 ? 1 ? 300 f 21 mf using six 330 f panasonic sp capacitors with a typical esr of 7 m each yields c x = 1.98 mf and r x = 1.2 m . ensure that the esl of the bulk capacitors (l x ) is low enough to limit the high frequency ringing during a load change. this is tested using: l x 300 f (2.1 m ) 2 2 2nh (eq. 13) l x c z r o 2 q 2 where: q is limited to the square root of 2 to ensure a critically damped system. l x is about 150 ph for the six sp capacitors, which is low enough to avoid ringing during a load change. if the l x of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. for this multimode control technique, an all ceramic capacitor design can be used if the conditions of equations 11, 12, and 13 are satisfied. power mosfets for typical 20 a per phase applications, the n ? channel power mosfets are selected for two high ? side switches and two or three low ? side switches per phase. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . because the voltage of the gate driver is 5.0 v, logic ? level threshold mosfets must be used. the maximum output current, i o , determines the r ds(on) requirement for the low ? side (synchronous) mosfets. in the apd3212/ncp3218/NCP3218G, currents are balanced between phases; the current in each low ? side mosfet is the output current divided by the total number of mosfets (n sf ). with conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous mosfet in terms of the ripple current per phase (i r ) and the average total output current (i o ): p sf (1 ? d) i o n sf 2 1 12 n i r n sf 2 r ds(sf) (eq. 14) where: d is the duty cycle and is approximately the output voltage divided by the input voltage. i r is the inductor peak ? to ? peak ripple current and is approximately i r (1 d) v out l f sw knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required r ds(on) for the mosfet. for 8 ? lead soic or 8 ? lead soic compatible mosfets, the junction ? to ? ambient (pcb) thermal impedance is 50 c/w. in the worst case, the pcb temperature is 70 c to 80 c during heavy load operation of the notebook, and a safe limit for p sf is about 0.8 w to 1.0 w at 120 c junction temperature. therefore, for this example (40 a maximum), the r ds(sf) per mosfet is less than 8.5 m for two pieces of low ? side mosfets. this r ds(sf) is also at a junction temperature of about 120 c; therefore, the r ds(sf) per mosfet should be less than 6 m at room temperature, or 8.5 m at high temperature. another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous mosfets when the switch node goes high. the high ? side (main) mosfet must be able to handle two main power dissipation components: conduction losses and switching losses. switching loss is related to the time for the main mosfet to turn on and off and to the current and voltage that are being switched. basing the switching speed on the rise and fall times of the gate driver impedance and mosfet input capacitance, the following expression provides an approximate value for the switching loss per main mosfet: p s(mf) 2 f sw v dc i o n mf r g n mf n c iss (eq. 15) where: n mf is the total number of main mosfets. r g is the total gate resistance. c iss is the input capacitance of the main mosfet. adp3212, ncp3218, NCP3218G http://onsemi.com 28 the most effective way to reduce switching loss is to use lower gate capacitance devices. the conduction loss of the main mosfet is given by the following equation: p c(mf) d i o n mf 2 1 12 n i r n mf 2 r ds(mf) (eq. 16) where r ds(mf) is the on resistance of the mosfet. typically, a user wants the highest speed (low c iss ) device for a main mosfet, but such a device usually has higher on resistance. therefore, the user must select a device that meets the total power dissipation (about 0.8 w to 1.0 w for an 8 ? lead soic) when combining the switching and conduction losses. for example, an irf7821 device can be selected as the main mosfet (four in total; that is, n mf = 4), with approximately c iss = 1010 pf (maximum) and r ds(mf) = 18 m (maximum at t j = 120 c), and an ir7832 device can be selected as the synchronous mosfet (four in total; that is, n sf = 4), with r ds(sf) = 6.7 m (maximum at t j = 120 c). solving for the power dissipation per mosfet at i o = 40 a and i r = 9.0 a yields 630 mw for each synchronous mosfet and 590 mw for each main mosfet. a third synchronous mosfet is an option to further increase the conversion efficiency and reduce thermal stress. finally, consider the power dissipation in the driver for each phase. this is best described in terms of the q g for the mosfets and is given by the following equation: p drv f sw 2 n (n mf q gmf n sf q gsf ) i cc vcc (eq. 17) where q gmf is the total gate charge for each main mosfet, and q gsf is the total gate charge for each synchronous mosfet. the previous equation also shows the standby dissipation (i cc times the vcc) of the driver. ramp resistor selection the ramp resistor (r r ) is used to set the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. use the following expression to determine a starting value: r r a r l 3 a d r ds c r (eq. 18) r r 0.5 360 nh 3 5 5.2 m 5pf 462 k where: a r is the internal ramp amplifier gain. a d is the current balancing amplifier gain. r ds is the total low ? side mosfet on resistance. c r is the internal ramp capacitor value. another consideration in the selection of r r is the size of the internal ramp voltage (see equation 19). for stability and noise immunity, keep the ramp size larger than 0.5 v. t aking this into consideration, the value of r r in this example is selected as 280 k . the internal ramp voltage magnitude can be calculated as follows: v r a r (1 d) v vid r r c r f sw (eq. 19) v r 0.5 (1 0.061) 1.150 v 462 k 5pf 280 khz 0.83 v the size of the internal ramp can be increased or decreased. if it is increased, stability and transient response improves but thermal balance degrades. conversely, if the ramp size is decreased, thermal balance improves but stability and transient response degrade. in the denominator of equation 18, the factor of 3 sets the minimum ramp size that produces an optimal combination of good stability, transient response, and thermal balance. current limit setpoint to select the current limit setpoint, the resistor value for r clim must be determined. the current limit threshold for the apd3212/ncp3218/NCP3218G is set with r clim . r clim can be found using the following equation: r lim i lim r o 60 a (eq. 20) where: r lim is the current limit resistor. r o is the output load line. i lim is the current limit setpoint. when the apd3212/ncp3218/NCP3218G is configured for 3 phase operation, the equation above is used to set the current limit. when the apd3212/ncp3218/NCP3218G switches from 3 phase to 1 phase operation by psi or dprslp signal, the current is single phase is one third of the current limit in 3 phase. when the apd3212/ncp3218/NCP3218G is configured for 2 phase operation, the equation above is used to set the current limit. when the apd3212/ncp3218/NCP3218G switches from 2 phase to 1 phase operation by psi or dprslp signal, the current is single phase is one half of the current limit in 2 phase. when the apd3212/ncp3218/NCP3218G is configured for 1 phase operation, the equation above is used to set the current limit. current monitor the apd3212/ncp3218/NCP3218G has output current monitor. the imon pin sources a current proportional to the total inductor current. a resistor, r mon , from imon to fbrtn sets the gain of the output current monitor. a 0.1 f is placed in parallel with r mon to filter the inductor current adp3212, ncp3218, NCP3218G http://onsemi.com 29 ripple and high frequency load transients. since the imon pin is connected directly to the cpu, it is clamped to prevent it from going above 1.15 v. the imon pin current is equal to the r lim times a fixed gain of 4. r mon can be found using the following equation: r mon 1.15 v r lim 4 r o i fs (eq. 21) where: r mon is the current monitor resistor. r mon is connected from imon pin to fbrtn. r lim is the current limit resistor. r o is the output load line resistance. i fs is the output current when the voltage on imon is at full scale. feedback loop compensation design optimized compensation of the apd3212/ncp3218/ NCP3218G allows the best possible response of the regulator?s output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and that is equal to the droop resistance (r o ). with the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling. with the multimode feedback structure of the apd3212/ncp3218/NCP3218G, it is necessary to set the feedback compensation so that the converter?s output impedance works in parallel with the output decoupling. in addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). a type iii compensator on the voltage feedback is adequate for proper compensation of the output filter. figure 31 shows the type iii amplifier used in the apd3212/ncp3218/NCP3218G. figure 32 shows the locations of the two poles and two zeros created by this amplifier. comp fb reference voltage voltage error amplifier adp3212 output voltage figure 31. voltage error amplifier r a c a c fb c b r fb figure 32. poles and zeros of voltage error amplifier 0 db gain frequency ? 20 db/dec ? 20 db/dec f z1 f p0 f p1 f z2 the following equations give the locations of the poles and zeros shown in figure 32: f z1 1 2 c a r a (eq. 22) f z2 1 2 c fb r fb (eq. 23) f p0 1 2 (c a c b ) r fb (eq. 24) f p1 c a c b 2 r a c b c a (eq. 25) the expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for pcb and component parasitic effects (see the tuning procedure for 12 section): r e n r o a d r ds r l v rt v vid (eq. 26) 2 l (1 (n d)) v rt n c x r o v vid t a c x (r o r ) l x r o r o r r x (eq. 27) t b (r x r r o ) c x (eq. 28) t c v rt l a d r ds 2 f sw v vid r e (eq. 29) t d c x c z r o 2 c x (r o r ) c z r o (eq. 30) where: r is the pcb resistance from the bulk capacitors to the ceramics and is approximately 0.4 m (assuming an 8 ? layer motherboard). r ds is the total low ? side mosfet for on resistance per phase. a d is 5. v rt is 1.25 v. l x is 150 ph for the six panasonic sp capacitors. adp3212, ncp3218, NCP3218G http://onsemi.com 30 the compensation values can be calculated as follows: c a n r o t a r e r b (eq. 31) r a t c c a (eq. 32) c b t b r b (eq. 33) c fb t d r a (eq. 34) the standard values for these components are subject to the tuning procedure described in the tuning procedure for 12 section. c in selection and input current di/dt reduction in continuous inductor ? current mode, the source current of the high ? side mosfet is approximately a square wave with a duty ratio equal to n v out /v in and an amplitude that is one ? n th of the maximum output current. to prevent large voltage transients, use a low esr input capacitor sized for the maximum rms current. the maximum rms capacitor current occurs at the lowest input voltage and is given by: i crms d i o 1 n d 1 (eq. 35) i crms 0.18 40 a 1 2 0.18 1 9.6 a where i o is the output current. in a typical notebook system, the battery rail decoupling is achieved by using mlc capacitors or a mixture of mlc capacitors and bulk capacitors. in this example, the input capacitor bank is formed by eight pieces of 10 f, 25 v mlc capacitors, with a ripple current rating of about 1.5 a each. rc snubber it is important in any buck topology to use a resistor ? capacitor snubber across the low side power mosfet. the rc snubber dampens ringing on the switch node when the high side mosfet turns on. the switch node ringing could cause emi system failures and increased stress on the power components and controller. the rc snubber should be placed as close as possible to the low side mosfet. typical values for the resistor range from 1 to 10 . typical values for the capacitor range from 330 pf to 4.7 nf. the exact value of the rc snubber depends on the pcb layout and mosfet selection. some fine tuning must be done to find the best values. the equation below is used to find the starting values for the rc subber. r snubber 1 2 f ringing c oss (eq. 36) c snubber 1 f ringing r snubber (eq. 37) p snubber c snubber v input 2 f switching (eq. 38) where r snubber is the snubber resistor. c snubber is the snubber capacitor. f rininging is the frequency of the ringing on the switch node when the high side mosfet turns on. c oss is the low side mosfet output capacitance at v input . this is taken from the low side mosfet data sheet. v input is the input voltage. f switching is the switching frequency. p snubber is the power dissipated in r snubber . selecting thermal monitor components to monitor the temperature of a single ? point hot spot, set r ttset1 equal to the ntc thermistor?s resistance at the alarm temperature. for example, if the alarm temperature for vrtt is 100 c and a vishey thermistor (nths ? 0603n011003j) with a resistance of 100 k at 25 c, or 6.8 k at 100 c, is used, the user can set r ttset1 equal to 6.8 k (the r th1 at 100 c). figure 33. single ? point thermal monitoring ttsns adp3212 vcc r 5 v vrtt r r th1 c tt r ttset1 to monitor the temperature of multiple ? point hot spots, use the configuration shown in figure 34. if any of the monitored hot spots reaches the alarm temperature, the vrtt signal is asserted. the following calculation sets the alarm temperature: r ttset1 1 2 v fd v ref 1 2 v fd v ref r th1alarmtemperature (eq. 39) where v fd is the forward drop voltage of the parallel diode. because the forward current is very small, the forward drop voltage is very low, that is, less than 100 mv. assuming the same conditions used for the single ? point thermal monitoring example?that is, an alarm temperature of 100 c and use of an nths ? 0603n011003j vishay thermistor?solving equation 39 gives a r ttset of 7.37 k , and the closest standard resistor is 7.32 k (1%). adp3212, ncp3218, NCP3218G http://onsemi.com 31 figure 34. multiple ? point thermal monitoring adp3212 ttsns + ? vcc 5 v vrtt r r c tt r th1 r th2 r ttset1 r ttset2 r th3 r ttset3 11 37 the number of hot spots monitored is not limited. the alarm temperature of each hot spot can be individually set by using different values for r ttset1 , r ttset2 , ... r ttsetn . tuning procedure for apd3212/ncp3218/NCP3218G set up and test the circuit 1. build a circuit based on the compensation values computed from the design spreadsheet. 2. connect a dc load to the circuit. 3. turn on the apd3212/ncp3218/NCP3218G and verify that it operates properly. 4. check for jitter with no load and full load conditions. set the dc load line 1. measure the output voltage with no load (v nl ) and verify that this voltage is within the specified tolerance range. 2. measure the output voltage with a full load when the device is cold (v flcold ). allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (v flhot ). if the difference between the two measured voltages is more than a few millivolts, adjust r cs2 using equation 40. r cs2(new) r cs2(old) v nl v flcold v nl v flhot (eq. 40) 3. repeat step 2 until no adjustment of r cs2 is needed. 4. compare the output voltage with no load to that with a full load using 5 a steps. compute the load line slope for each change and then find the average to determine the overall load line slope (r omeas ). 5. if the difference between r omeas and r o is more than 0.05 m , use the following equation to adjust the r ph values: r ph(new) r ph(old) r omeas r o (eq. 41) 6. repeat steps 4 and 5 until no adjustment of r ph is needed. once this is achieved, do not change r ph , r cs1 , r cs2 , or r th for the rest of the procedure. 7. measure the output ripple with no load and with a full load with scope, making sure both are within the specifications. set the ac load line 1. remove the dc load from the circuit and connect a dynamic load. 2. connect the scope to the output voltage and set it to dc coupling mode with a time scale of 100 s/div. 3. set the dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 4. measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). try to use a vertical scale of 100 mv/div or finer. 5. the resulting waveform will be similar to that shown in figure 35. use the horizontal cursors to measure v acdrp and v dcdrp , as shown in figure 35. do not measure the undershoot or overshoot that occurs immediately after the step. figure 35. ac load line waveform v dcdrp v acdrp 6. if the difference between v acdrp and v dcdrp is more than a couple of millivolts, use equation 42 to adjust c cs . it may be necessary to try several parallel values to obtain an adequate one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason). c cs(new) c cs(old) v acdrp v dcdrp (eq. 42) 7. repeat steps 5 and 6 until no adjustment of c cs is needed. once this is achieved, do not change c cs for the rest of the procedure. 8. set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning v acdrp and v dcdrp are equal. 9. ensure that the load step slew rate and the powerup slew rate are set to ~150 a/ s to 250 a/ s (for example, a load step of 50 a should take 200 ns to 300 ns) with no overshoot. some adp3212, ncp3218, NCP3218G http://onsemi.com 32 dynamic loads have an excessive overshoot at powerup if a minimum current is incorrectly set (this is an issue if a vtt tool is in use). set the initial transient 1. with the dynamic load set at its maximum step size, expand the scope time scale to 2 s/div to 5 s/div. this results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after v droop (see figure 36). figure 36. transient setting waveform, load step v tran1 v droop v tran2 2. if both overshoots are larger than desired, try the following adjustments in the order shown. a. increase the resistance of the ramp resistor (r ramp ) by 25%. b. for v tran1 , increase c b or increase the switching frequency. c. for v tran2 , increase r a by 25% and decrease c a by 25%. if these adjustments do not change the response, it is because the system is limited by the output decoupling. check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable. 3. for load release (see figure 37), if v tranrel is larger than the value specified by imvp ? 6.5, a greater percentage of output capacitance is needed. either increase the capacitance directly or decrease the inductor values. (if inductors are changed, however, it will be necessary to redesign the circuit using the information from the spreadsheet and to repeat all tuning guide procedures). figure 37. transient setting waveform, load release v tranrel v droop layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations 1. for best results, use a pcb of four or more layers. this should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 m at room temperature. 2. when high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. if critical signal lines (including the output voltage sense lines of the apd3212/ncp3218/ NCP3218G) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise. 4. an analog ground plane should be used around and under the apd3212/ncp3218/NCP3218G for referencing the components associated with the controller. this plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane. adp3212, ncp3218, NCP3218G http://onsemi.com 33 5. the components around the apd3212/ncp3218/ NCP3218G should be located close to the controller with short traces. the most important traces to keep short and away from other traces are those to the fb and cssum pins. refer to figure 30 for more details on the layout for the cssum node. 6. the output capacitors should be connected as close as possible to the load (or connector) that receives the power (for example, a microprocessor core). if the load is distributed, the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic. 7. avoid crossing signal lines over the switching power path loop, as described in the power circuitry section. 8. connect a 1 f decoupling ceramic capacitor from vcc to gnd. place this capacitor as close as possible to the controller. connect a 4.7 f decoupling ceramic capacitor from pvcc to pgnd. place capacitor as close as possible to the controller. power circuitry 1. the switching power path on the pcb should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise ? related operational problems in the power ? converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets, including all interconnecting pcb traces and planes. the use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. 2. when a power ? dissipating component (for example, a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the pcb, where a plane can more readily transfer heat to the surrounding air. to achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the mosfets on the opposite side of the pcb. in addition, improvements in thermal performance can be obtained using the largest possible pad area. 3. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. 4. for best emi containment, a solid power ground plane should be used as one of the inner layers and extended under all power components. signal circuitry 1. the output voltage is sensed and regulated between the fb and fbrtn pins, and the traces of these pins should be connected to the signal ground of the load. to avoid differential mode noise pickup in the sensed signal, the loop area should be as small as possible. therefore, the fb and fbrtn traces should be routed adjacent to each other, atop the power ground plane, and back to the controller. 2. the feedback traces from the switch nodes should be connected as close as possible to the inductor. the csref signal should be kelvin connected to the center point of the copper bar, which is the v core common node for the inductors of all the phases. 3. on the back of the apd3212/ncp3218/ NCP3218G package, there is a metal pad that can be used to heat sink the device. therefore, running vias under the apd3212/ncp3218/NCP3218G is not recommended because the metal pad may cause shorting between vias. ordering information device number* temperature range package package option shipping ? adp3212mnr2g ? 40 c to 100 c 48 ? lead frame chip scale pkg [qfn_vq] 7x7 mm, 0.5 mm pitch cp ? 48 ? 1 2500 / tape & reel ncp3218mnr2g ? 40 c to 100 c 48 ? lead frame chip scale pkg [qfn_vq] 6x6 mm, 0.4 mm pitch cp ? 48 ? 1 2500 / tape & reel ncp3218mntwg ? 40 c to 100 c 48 ? lead frame chip scale pkg [qfn_vq] 6x6 mm, 0.4 mm pitch cp ? 48 ? 1 2500 / tape & reel NCP3218Gmnr2g ? 40 c to 100 c 48 ? lead frame chip scale pkg [qfn_vq] 6x6 mm, 0.4 mm pitch cp ? 48 ? 1 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. *the ?g?? suffix indicates pb ? free package. adp3212, ncp3218, NCP3218G http://onsemi.com 34 package dimensions qfn48 7x7, 0.5p case 485aj issue o note 3 seating plane k 0.15 c (a3) a a1 d2 b 1 13 25 48 37 2x 2x e2 48x 12 36 l 48x bottom view top view side view 0.15 c d a b e pin 1 location 0.08 c 0.05 c e 0.10 c 0.05 c a b c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to the plated terminal and is measured abetween 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 7.00 bsc d2 5.00 5.20 e 7.00 bsc e2 5.00 5.20 e 0.50 bsc k 0.20 ??? l 0.30 0.50 note 4 l detail a optional construction 2x scale detail a e/2 dimensions: millimeters 0.50 pitch 5.20 0.30 48x 7.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 2x 2x 0.63 48x adp3212, ncp3218, NCP3218G http://onsemi.com 35 package dimensions qfn48 6x6, 0.4p case 485ba issue a seating note 4 k 0.10 c (a3) a a1 d2 b 1 13 25 48 2x 2x e2 48x l bottom view detail a top view side view d a b e 0.10 c pin one location 0.10 c 0.08 c c 37 e a 0.07 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.40 4.60 e 6.00 bsc 4.60 e2 4.40 e 0.40 bsc l 0.30 0.50 l1 0.00 0.15 note 3 plane dimensions: millimeters 0.25 4.66 0.40 4.66 48x 0.68 48x 6.40 6.40 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* e/2 detail b l1 detail a l alternate terminal constructions l 0.20 min pitch 48x pkg outline on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. adp3212/d all brand names and product names appearing in this document are registered trademarks or trademarks of their respective holder s. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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